Category: cpu

I have been reading this book during my lunch brakes for several month. Most of the times just a couple of pages to be honest as generally my knowledge of CPU architecture is very poor. I really enjoyed this subject in Uni and this book was one of my favourites during that time. It was like a bible of CPU architecture. And Patterson is an author in both books.

I remember that there were too main architectures RISC vs CISC. In a very summarize way, RISC were simple instruction that were easy to parallelized and executed (with more instructions to execute) and CISC were complex instruction (few to execute) but that were difficult to scale. So let’s say simplicity (RISC) “won” the race in CPU architecture.

RISC-V is an open standard so anybody can produce CPUs for executing those instruction. So you can easily get your hands dirty getting a board.

One of the reason of RISC-V is to learn from all the architectures mistakes and provide a design that works for any type of processor (embedded to super-computers), is efficient, modular and stable.

The book compares RISC-V with current ISAS from ARM-32, MIPS-32, Intel x86-32, etc. Based on cost, simplicity, performance , isolation from implementation, room for growth, code size and ease of programming.

There were many parts of the book that I couldn’t really understand but I found the chapter 8 quite interesting. This is about how to compute data concurrently. The best know architecture is Single Instruction Multiple Data (SIMD). The alternative is Vector architecture. And this is used in RISC-V. The implementation details are too our of my league.

In summary, it was a nice read to refresh a bit my CPU architecture knowledge.